Multiple-path execution for chip multiprocessors

The increased dependence of clock cycle time on interconnect delay favors chip multiprocessors (CMP) as the basis for future microprocessor designs. The tight coupling of processing units in a CMP allows new forms of parallelism to be exploited. This paper studies multiple-path execution (MPE) on a CMP design to provide speedup on unmodified sequential code by exploring different paths of a conditional branch on separate processors. The impact on MPE performance due to processor complexity and count, cache and branch prediction architecture, processor-to-path allocation strategies, and interprocessor communication latency are explored. Simulation shows an achievable 24% speedup on SPECint95 with up to 51% on components with poor branch prediction accuracy.